A semiconductor memory having a rewritable non-volatile memory has been increasingly demanded as a memory card. In a NAND-type flash memory which is a non-volatile memory mainly used in the memory card, 16 KB has been employed as the erase unit. Therefore, an external host device using the memory card employs a size of 16 KB as its management unit for writing.
However recently, in order to increase the capacity of the memory card, the capacity of the incorporated NAND-type flash memory has been increasing and accordingly, a NAND-type flash memory employing 128 KB as its erase unit has been proposed. However, there is a defect that it relatively takes longer time to write data in units of 16 KB compared to the host device since a controller in the memory card deals the writing in units of 16 KB of the host device with the writing in units of 128 KB which are erase unit of the NAND type flash memory.
Next, a conventional semiconductor memory card will be described in detail. FIG. 1 shows a conventional memory card 100 provided with a controller 101 and flash memories FM0 to FM3 which are non-volatile memories. Each of the flash memories FM0 to FM3, for example, has capacity of 128 MB, for example and constitutes a memory card of 500 MB as a valid data region. In addition, as shown in FIG. 1, the controller 101 includes a CPU 111, a temporally save buffer 112 having capacity of 2 KB, a data transfer buffer 113 having capacity of 512B, an address conversion table 114 having 4 KWord by 12 bits, that is, capacity of 6 KB, and an entry table 115 having 4 KWord by 1 bit, that is, whole capacity of 512 B.
As shown in FIG. 1, each of the flash memories FM0 to FM3 has capacity of 128 MB. As shown in FIG. 2A, each of the flash memories FM0 to FM3 consists of 1024 physical blocks (PB0 to PB1023) each having capacity of 128 KB. Thus, although the whole capacity of the non-volatile memory of the memory card 100 becomes 512 MB, capacity that a host device 102 can use as a data region is 500 MB.
FIG. 2B shows a constitution of one physical block PBi (i=0 to 1023) in the flash memory. The physical block consists of 64 physical pages PP0 to PP63. Each physical page consists of a data region having capacity of 2 KB and a management region having capacity of 64B as shown in FIG. 3.
Thus, the memory card 100 has memory capacity of 500 MB as viewed from the external host device 102, in which logical addresses are assigned by a logical map as shown in FIG. 4. That is, the data region of 500 MB is divided into 4000 logical blocks (LB) from a logical block LB0 to a logical block LB3999, and each logical block has capacity of 128 KB. This logical block address corresponds to an address designated by the host device.
The address conversion table 114 shown in FIG. 1 specifies the flash memory and the physical block therein when the logical address showing the logical group is given. The first 2 bits specify any one of the flash memories FM0 to FM3, and the following 10 bits specify any one of the physical blocks in the flash memory. The entry table 115 consists of 1-bit flag corresponding to the 4096 physical blocks. These flags are set to 1 after data are erased and set to 0 after data are written.
Next, a data read process will be described with reference to a schematic view of data read in FIG. 5. In the logical address (LA) from the host device 102, an address in units of 128 KB is set to a logical block address (LBA) and an address less than 128 KB is set to a logical page address (LPA). The physical block PB is specified from the address conversion table 114 based on the logical block address and this is set to a read source physical block. Then, the data of the logical page address in the read source physical block is read and transferred to the host device 102 through the data transfer buffer 113. Then, it is checked whether the reading is completed or not and when it is not, it is checked whether the logical page address is the last one in the block or not. When it is not the last one, the logical page address is incremented and the same operations are repeated. When the logical page address is the last one in the block, the logical page address is set to 0 and the logical block address is incremented and the same operations are repeated. Thus, the data can be read from the designated logical address.
Next, a write process will be described with reference to a flowchart shown in FIG. 6. When the data is written, the logical address LA from the host device 102 is divided into a logical block address (LAB) for an address of 128 KB and a logical page address (LPA) for an address less than 128 KB in step S301. Then, in step S302, the entry table is searched and an erased physical block is obtained to be set to a write destination physical block (PB). Then, the corresponding bit of the entry table 115 is updated to 0. Then, in step S303, it is checked whether the logical page address LPA is 0 or not, and when it is not, a first-half evacuation process is performed as will be described below (step S304). When the logical page address is 0, the operation proceeds to step S305 without performing the process. Then, in step S305, the write data from the host device 102 is transferred to the flash memory through the page buffer, and it is written in the logical page address of the write destination physical block. At this time, management information to be written in a management region is simultaneously written. Then, in step S306, it is checked whether the writing is completed or not and, when it is not, it is checked whether the logical page address (LPA) is the last one in the block or not in step S307. When it is not the last one, the logical page address LPA is incremented in step S308 and the operation is returned to step S305. Meanwhile, when the logical page address is the last block, erase and table updating are performed in step S309 and the logical page address LPA is set to 0 and the logical block address LBA is incremented in step S310 and the process is returned to step S302. When writing is completed in step S306, it is checked whether the logical page address is the last one in the block or not in step S311. When it is not the last one, a second-half evacuation process is performed in step S312. Meanwhile, when it is the last one in the block, erase and table updating are performed in step S313 without performing step S312, and the process is completed.
According to the data write method of the conventional non-volatile memory device, as the read source physical block 120 has 128 KB, even when new data 122 of 16 KB which is managed by the host device is written, the write destination physical block 121 writes the data in units of 128 KB as shown in FIG. 7. In the read source physical block 120, a first-half region 120-1 which is not written in the physical block is copied in a write destination physical block 121-1 of the flash memory by the first-half evacuation process. Similarly, a second-half region 120-2 is copied in a write destination physical block 121-2 according to the logical page address after the write page address by the second-half evacuation process. Therefore, according to the conventional data write process, even when the data process unit managed by the external host device is 16 KB as shown in FIG. 7, the data is written in units of physical blocks of the write destination.
Thus, according to the data write method of the conventional non-volatile memory device, when data having a size smaller than an erase size of the flash memory is written, since data equal to the erase size of the flash memory is written in the memory card, there is a defect that a write speed is lowered.
The present invention has been made in view of the conventional problem and it is an object of the present invention to make it possible to perform a write process at high speed by reducing the write unit, to assure an erased block by collecting written data, and to facilitate the next write in the assured erased region.